The present invention relates to a circuit for controlling termination impedance, more particularly to a calibration circuit of an on die termination (ODT) device, which can generate a calibration code through a fast calibration operation.
Semiconductor devices, for example, central processing units (CPUs), memories, and gate arrays, which are implemented with integrated circuit (IC) chips, are incorporated into a variety of electrical products such as personal computers, servers and workstations. Most semiconductor devices include an input circuit configured to receive signals from the outside world via input pads and an output circuit configured to provide internal signals to the outside via output pads.
As the operating speed of electrical products has increased, the swing width (that is the difference between high and low logic levels) of a signal interfaced between semiconductor devices gradually has been reduced in order to minimize a delay time taken for signal transmission. However, the reduction in the swing width of the signal easily exposes the signal to external noise, causing signal reflection to become more critical at an interface terminal due to impedance mismatch. Such impedance mismatch is generally caused by external noise, a variation of a power supply voltage, a change in operating temperature, a change in a manufacturing process, etc. The impedance mismatch may lead to a difficulty in high-speed transmission of data and distortion of output data. Therefore, if semiconductor devices receive the distorted output signal through an input terminal, this frequently gives rise to problems such as a setup/hold failure and an error in a decision as to an input level.
In particular, in order to resolve the above problems, a memory device requiring high-speed performance employs an impedance matching circuit, which is called an ODT device, near an input pad inside an IC chip. In a typical ODT scheme, source termination is performed at a transmitting end by an output circuit, and parallel termination is performed by a termination circuit connected in parallel with respect to an input circuit.
To match the termination impedance, the resistance of the ODT device, e.g., a termination resistance at a DQ (data) pad in a memory device, is calibrated using calibration codes. The calibration codes result from ZQ calibration, which is a procedure for generating calibration codes that varies with process, voltage and temperature (PVT) conditions. The ZQ calibration is referred to as such because the calibration is performed using a ZQ node, which is a node for calibration.
A calibration circuit of the conventional ODT device for generating the calibration codes will be described below.
FIG. 1 is a circuit diagram of a conventional calibration circuit of an ODT device.
Referring to FIG. 1, the conventional calibration circuit includes a code generation unit 120 and a calibration resistor unit 110.
The code generation unit 120 generates a calibration code CODE<0:N> in response to a voltage of a calibration node ZQ and a reference voltage
      (          generally      ⁢                          ⁢              VDDQ        2              )    .The code generation unit 120 includes a comparison unit 121, a counting unit 122, and a transfer unit 123. The comparison unit 121 compares the voltage of the calibration node ZQ with the reference voltage VREF to generate an up/down signal. The comparison unit 121 performs the comparison operation when the enable signal ENABLE is in an activated state, while it does not operate when the enable signal ENABLE is in a deactivated state.
The counting unit 122 increases or decreases the calibration code CODE<0:N> in response to the up/down signal output from the comparison unit 121. The counting unit 122 increases or decreases the calibration code CODE<0:N> in response to the output of the comparison unit 121 when the enable signal ENABLE is in the activated state, but it stops increasing or decreasing the calibration code CODE<0:N> and maintains the final code value when the enable signal ENABLE is in the deactivated state.
The transfer unit 123 transfers the calibration code CODE<0:N> to the calibration resistor unit 110 without change when the enable signal ENABLE is activated. On the other hand, the transfer unit 123 disables the calibration code CODE<0:N> and transfers the disabled calibration code CODE<0:N> when the enable signal ENABLE is deactivated. The disabling of the calibration code CODE<0:N> means that all resistors of the calibration resistor unit 110 are disconnected. Since transistors included in the calibration resistor unit 110 are PMOS transistors, the disabling of the calibration code CODE<0:N> means that the calibration code CODE<0:N> has a value of <1,1,1,1, . . .>.
The calibration resistor unit 110 drives the calibration node ZQ while the parallel transistors are turned on/off in response to the calibration code CODE<0:N>. As described above, when the code generation unit 120 is disabled, that is, the enable signal ENABLE is deactivated, the transfer unit 123 disables the calibration code CODE<0:N> and transfers the disabled calibration code CODE<0:N> to the calibration resistor unit 110. Therefore, when the enable signal ENABLE is deactivated, all the parallel transistors of the calibration resistor unit 110 are turned off.
An operation of the code generation unit 120 at enabled state, that is, when the enable signal ENABLE is activated, will be described below. Since the transfer unit 123 merely transfers the calibration code CODE<0:N> of the counting unit 122 to the calibration resistor unit 110 when the enable signal ENABLE is activated, detailed description thereof will be omitted.
The comparison unit 121 compares the reference voltage VREF with the voltage of the calibration node ZQ, which varies according to the resistance ratio of the external resistor 101 to the calibration resistor unit 110, to generate the up/down signal. The counting unit 122 increases or decreases the calibration code CODE<0:N> according to the up/down signal. The decreased calibration code CODE<0:N> is input to the calibration resistor unit 110 to change a total resistance of the calibration resistor unit 110. The changed total resistance of the calibration resistor unit 110 also changes the voltage of the calibration node ZQ. This operation is repeated until the voltage of the calibration node ZQ is equal to the reference voltage VREF.
That the voltage of the calibration node ZQ is equal to the reference voltage VREF means that the total resistance of the calibration resistor unit 110 is equal to the resistance of the external resistor 101. The calibration code CODE<0:N> generated in the above manner is transferred to a termination resistor unit (not shown), which is located at an input/output pad and configured with the same as the calibration resistor unit 110, and determines the termination resistance of the ODT device.
When the code generation unit 120 is disabled, that is, the enable signal ENABLE is deactivated, the comparison unit 121 and the counting unit 122 do not perform the operation of increasing or decreasing the calibration code CODE<0:N> any more. However, the counting unit 122 maintains the value of the calibration code CODE<0:N> that is obtained before it is disabled. This is done for starting the calibration operation from the previous calibration code CODE<0:N> when the code generation unit 120 is again enabled.
When the code generation unit 120 is disabled, the transfer unit 123 disables the calibration code CODE<0:N> and transfers the disabled calibration code CODE<0:N> to the calibration resistor unit 110. Therefore, all the parallel transistors of the calibration resistor unit 110 are turned off. This is done for preventing unnecessary current consumption by blocking current flowing from the calibration resistor unit 110 to the external resistor 101.
Since the external resistor 101 is disposed outside the semiconductor device chip, a dummy capacitor having a large capacitance exists in the external resistor. Therefore, when the disabled code generation unit 120 and calibration resistor unit 110 are again enabled to restart the calibration operation, the voltage of the calibration node ZQ moves very late. That is, when the calibration resistor unit 110 is again enabled, the calibration node ZQ does not immediately reach the voltage given by the resistance ratio of the calibration resistor unit 110 to the external resistor 101, but reaches the desired voltage after a delay time due to the dummy capacitor elapses.
When the calibration circuit intends to restart the calibration operation, the delay time always occurs due to the dummy capacitor existing in the external resistor 101 and thus time necessary for the calibration operation is lengthened.